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FINAL
COM'L: -7.5/10/12/15/20
IND: -10/12/14/18/24
MACH211SP-7/10/12/15/20
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
s JTAG-Compatible, 5-V in-system programming s 44 Pins s 64 Macrocells s 7.5 ns tPD Commercial 10 ns tPD Industrial s 133 MHz fCNT s 34 Bus-FriendlyTM Inputs and I/Os s Peripheral Component Interconnect (PCI) compliant (-7/-10) s Programmable power-down mode s s s s 32 Outputs 64 Flip-flops; 2 clock choices 4 "PAL26V16" blocks with buried macrocells Improved routing over the MACH210
IN-SYSTEM PROGRAMMING
In-system programming allows the MACH211SP to be programmed while soldered onto a system board. Programming the MACH211SP in-system yields numerous benefits at all stages of development: prototyping, manufacturing, and in the field. Since insertion into a programmer isn't needed, multiple handling steps and the resulting bent leads are eliminated. The design can be modified in-system for design changes and debugging while prototyping, programming boards in production, and field upgrades. The MACH211SP offers advantages not available in other CPLD architectures with in-system programming. MACH devices have extensive routing resources for pin-out retention; design changes resulting in pin-out changes for other CPLDs cancel the advantages of in-system programming. The MACH211SP can be employed in any JTAG (IEEE 1149.1) compliant chain.
GENERAL DESCRIPTION
The MACH211SP is a member of AMD's EE CMOS Performance Plus MACH(R) 2 device family. This device has approximately six times the logic macrocell capability of the popular PAL22V10 without loss of speed. The MACH211SP consists of four PAL(R) blocks interconnected by a programmable switch matrix. The four PAL blocks are essentially "PAL26V16" structures complete with product-term arrays and programmable macrocells, which can be programmed as high speed or low power, and buried macrocells. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACH211SP has two kinds of macrocell: output and buried. The MACH211SP output macrocell provides registered, latched, or combinatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. All output macrocells can be connected to an I/O cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input. The MACH211SP has dedicated buried macrocells which, in addition to the capabilities of the output macrocell, also provide input registers or latches for use in synchronizing signals and reducing setup time requirements. The MACH211SP is an enhanced version of the MACH211, adding the JTAG-compatible in-system programming feature.
Publication# 20405 Rev: B Amendment/0 Issue Date: February 1996
BLOCK DIAGRAM
I/O0-I/O7 8 I/O Cells 8 Macrocells 8 8 Macrocells I/O Cells 8 Macrocells I/O8-I/O15 8 8 8 Macrocells 2
OE 52 x 68 AND Logic Array and Logic Allocator 26 Switch Matrix 26 52 x 68 AND Logic Array and Logic Allocator OE Macrocells 8 I/O Cells 8 8 Macrocells 8
OE 52 x 68 AND Logic Array and Logic Allocator 26
26 52 x 68 AND Logic Array and Logic Allocator OE Macrocells 8 I/O Cells 8 8 Macrocells 8
2
2
I/O24-I/O31
I/O16-I/O23
CLK0/I0 CLK1/I1
20405B-1
2
MACH211SP-7/10/12/15/20
CONNECTION DIAGRAM MACH211SP Top View 44-Pin PLCC
I/O31
I/O30
I/O29
6 I/O5 I/O6 I/O7 TDI CLK0/I0 GND TCK I/O8 I/O9 I/O10 I/O11 7 8 9 10 11 12 13 14 15 16 17
54
32
1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 I/O27 I/O26 I/O25 I/O24 TDO GND CLK1/I1 TMS I/O23 I/O22 I/O21
18 19 20 21 22 23 24 25 26 27 28 I/O12 I/O13 I/O14 I/O15 GND I/O16 I/O17 I/O18 I/O19 I/O20 VCC
I/O28
GND
I/O4
I/O3
I/O2
I/O1
I/O0
VCC
20405B-2
PIN DESIGNATIONS
CLK/I = Clock or Input GND = Ground I I/O = Input = Input/Output TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out
VCC = Supply Voltage
MACH211SP-7/10/12/15/20
3
CONNECTION DIAGRAM MACH211SP Top View 44-Pin TQFP
I/O5 I/O6 I/O7 TDI CLK0/I0 GND TCK I/O8 I/O9 I/O10 I/O11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O31 I/O30 I/O29 I/O28
I/O27 I/O26 I/O25 I/O24 TDO GND CLK1/I1 TMS I/O23 I/O22 I/O21
I/O12 I/O13 I/O14 I/O15 VCC GND I/O16 I/O17 I/O18 I/O19 I/O20
20405B-3
PIN DESIGNATIONS
CLK/I = Clock or Input GND = Ground I I/O VCC = Input = Input/Output = Supply Voltage TDI = Test Data In TCK = Test Clock TMS = Test Mode Select TDO = Test Data Out
4
MACH211SP-7/10/12/15/20
ORDERING INFORMATION Commercial Products
AMD programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of:
MACH
211
SP
-7
J
C
FAMILY TYPE MACH = Macro Array CMOS High-Speed
OPTIONAL PROCESSING Blank = Standard Processing
DEVICE NUMBER 211 = 64 Macrocells, 44 Pins, Power-Down mode, Bus-Friendly Inputs and I/Os PRODUCT DESIGNATION SP = In-system Programmable
OPERATING CONDITIONS C = Commercial (0C to +70C)
PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044) V = 44-Pin Thin Quad Flat Pack (PQT044) SPEED -7 = 7.5 ns tPD -10 = 10 ns tPD -12 = 12 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD
Valid Combinations MACH211SP-7 MACH211SP-10 MACH211SP-12 MACH211SP-15 MACH211SP-20 JC, VC
Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
MACH211SP-7/10/12/15/20 (Com'l)
5
ORDERING INFORMATION Industrial Products
AMD programmable logic products for industrial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of:
MACH
211
SP
-10
J
I
FAMILY TYPE MACH = Macro Array CMOS High-Speed
OPTIONAL PROCESSING Blank = Standard Processing
DEVICE NUMBER 211 = 64 Macrocells, 44 Pins, Power-Down mode, Bus-Friendly Inputs and I/Os PRODUCT DESIGNATION SP = In-system Programmable
OPERATING CONDITIONS I = Industrial (-40C to +85C)
PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044)
SPEED -10 = 10 ns tPD -12 = 12 ns tPD -14 = 14.5 ns tPD -18 = 18 ns tPD -24 = 24 ns tPD
Valid Combinations MACH211SP-10 MACH211SP-12 MACH211SP-14 MACH211SP-18 MACH211SP-24 JI
Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
6
MACH211SP-10/12/14/18/24 (Ind)
FUNCTIONAL DESCRIPTION
The MACH211SP consists of four PAL blocks connected by a switch matrix. There are 32 I/O pins feeding the switch matrix. These signals are distributed to the four PAL blocks for efficient design implementation. There are two clock pins that can also be used as dedicated inputs.
Output M0
Table 1.
Macrocell Buried
Logic Allocation
Available Clusters C0, C1, C2
M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15
C0, C1, C2, C3 C1, C2, C3, C4 C2, C3, C4, C5 C3, C4, C5, C6 C4, C5, C6, C7 C5, C6, C7, C8 C6, C7, C8, C9 C7, C8, C9, C10 C8, C9, C10, C11 C9, C10, C11, C12 C10, C11, C12, C13 C11, C12, C13, C14 C12, C13, C14, C15 C13, C14, C15 C14, C15
The PAL Blocks
Each PAL block in the MACH211SP (Figure 1) contains a 64-product-term logic array, a logic allocator, 8 output macrocells, 8 buried macrocells, and 8 I/O cells. The switch matrix feeds each PAL block with 26 inputs. This makes the PAL block look effectively like an independent "PAL26V16" with 8 buried macrocells. In addition to the logic product terms, two output enable product terms, an asynchronous reset product term, and an asynchronous preset product term are provided. One of the two output enable product terms can be chosen within each I/O cell in the PAL block. All flip-flops within the PAL block are initialized together.
The Switch Matrix
The MACH211SP switch matrix is fed by the inputs and feedback signals from the PAL blocks. Each PAL block provides 16 internal feedback signals and 8 I/O feedback signals. The switch matrix distributes these signals back to the PAL blocks in an efficient manner that also provides for high performance. The design software automatically configures the switch matrix when fitting a design into the device.
feedback whether configured with or without the flip-flop. The registers can be configured as D-type or T-type, allowing for product-term optimization. The flip-flops can individually select one of two clock/ gate pins, which are also available as data inputs. The registers are clocked on the LOW-to-HIGH transition of the clock signal. The latch holds its data when the gate input is HIGH, and is transparent when the gate input is LOW. The flip-flops can also be asynchronously initialized with the common asynchronous reset and preset product terms. The buried macrocells are the same as the output macrocells if they are used for generating logic. In that case, the only thing that distinguishes them from the output macrocells is the fact that there is no I/O cell connection, and the signal is only used internally. The buried macrocell can also be configured as an input register or latch.
The Product-term Array
The MACH211SP product-term array consists of 64 product terms for logic use, and 4 special-purpose product terms. Two of the special-purpose product terms provide programmable output enable; one provides asynchronous reset, and one provides asynchronous preset.
The Logic Allocator
The logic allocator in the MACH211SP takes the 64 logic product terms and allocates them to the 16 macrocells as needed. Each macrocell can be driven by up to 16 product terms. The design software automatically configures the logic allocator when fitting the design into the device. Table 1 illustrates which product term clusters are available to each macrocell within a PAL block. Refer to Figure 1 for cluster and macrocell numbers.
The I/O Cell
The I/O cell in the MACH211SP consists of a three-state output buffer. The three-state buffer can be configured in one of three ways: always enabled, always disabled, or controlled by a product term. If product term control is chosen, one of two product terms may be used to provide the control. The two product terms that are available are common to all I/O cells in a PAL block.
The Macrocell
The MACH211SP has two types of macrocell: output and buried. The output macrocells can be configured as either registered, latched, or combinatorial, with programmable polarity. The macrocell provides internal
MACH211SP-7/10/12/15/20
7
These choices make it possible to use the macrocell as an output, an input, a bidirectional pin, or a three-state output for use in driving a bus.
should be programmed. The configuration file is discussed in detail in the MACHPRO software manual. The MACH211SP devices tristate the outputs during programming. They have one security bit which inhibits program and verify. This allows the user to protect proprietary patterns and designs. Program verification of a MACH device involves reading back the programmed pattern and comparing it with the original JEDEC file. The AMD method of program verification performed on the MACH devices permits the verification of one device at a time.
Power-Down Mode
The MACH211SP features a programmable low-power mode in which individual signal paths can be programmed as low power. These low-power speed paths will be slightly slower than the non-low-power paths. This feature allows speed critical paths to run at maximum frequency while the rest of the paths operate in the low-power mode, resulting in power savings of up to 75%. If all signals in a PAL block are low-power, then total power is reduced further.
In-System Programming
Programming is the process where MACH devices are loaded with a pattern defined in a JEDEC file obtained from MACHXL software or third-party software. Programming is accomplished through four JTAG pins: Test Mode Select (TMS), Test Clock (TCK), Test Data In (TDI), and Test Data Out (TDO). The MACH211SP can be employed in any JTAG (IEEE 1149.1) compliant chain. While the MACH211SP is fully JTAG compatible, it supports the BYPASS instruction, not the EXTEST and SAMPLE/PRELOAD instructions. The MACH211SP can be programmed across the commercial temperature range. Programming the MACH device after it has been placed on a circuit board is easily accomplished. Programming is initiated by placing the device into programming mode, using the MACHPRO programming software provided by AMD. The device is bulk erased and the JEDEC file is then loaded. After the data is transferred into the device, the PROGRAM instruction is loaded. Further programming details can be found in application note, "Advanced In-circuit Programming Guidelines."
Accidental Programming or Erasure Protection
It is virtually impossible to program or erase a MACH device inadvertently. The following conditions must be met before programming actually takes place: s The device must be in the password-protected program mode s The programming or bulk erase instruction must be in the instruction register If the above conditions are not met, the programming circuitry cannot be activated. To ensure that the AMD ten year device data retention guarantee applies, 100 program/erase cycle limit should not be exceeded.
Bus-Friendly Inputs and I/Os
The MACH211SP inputs and I/Os include two inverters in series which loop back to the input. This double inversion reinforces the state of the input and pulls the voltage away from the input threshold voltage. For an illustration of this configuration, please turn to the Input/Output Equivalent Schematics section.
On-Board Programming Options
Since the MACHPRO software performs these steps automatically, the following programming options are published for reference. The configuration file, which is also known as the chain file, defines the MACH device JTAG chain. The file contains the information concerning which JEDEC file is to be placed into which device, the state which the outputs should be placed, and whether the security fuses
PCI Compliance
The MACH211SP-7/10 is fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The MACH211SP-7/10's predictable timing ensures compliance with the PCI AC specifications independent of the design. On the other hand, in CPLD and FPGA architectures without predictable timing, PCI compliance is dependent upon routing and product term distribution.
8
MACH211SP-7/10/12/15/20
0
4
8
12
16
20
24
28
32
36
40
43
47
51 Output Enable Output Enable Asynchronous Reset Asynchronous Preset
M0
Output Macro Cell
I/O Cell
I/O
M1
Buried Macro Cell
M2
Output Macro Cell
I/O Cell
I/O
M3
0
Buried Macro Cell
C0 C1 C2 C3 C4 C5 Logic Allocator
I/O Cell
M4
Output Macro Cell
I/O
M5
Buried Macro Cell
I/O Cell
I/O
M6
Output Macro Cell
Switch Matrix
C6 C7 C8 C9
M7
Buried Macro Cell
M8
Output Macro Cell
I/O Cell
I/O
C10 C11 C12 C13 C14 C15
63
M9
Buried Macro Cell
M10
Output Macro Cell
I/O Cell
I/O
M11
Buried Macro Cell
M12
Output Macro Cell
I/O Cell
I/O
M13
Buried Macro Cell
I/O Cell
I/O
M14
Output Macro Cell
M15
CLK
Buried Macro Cell
2
0
4
8 16
12
16
20
24
28
32
36
40
43
47
51
8
20405B-4
Figure 1.
MACH211SP PAL Block
MACH211SP-7/10/12/15/20
9
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied. . . . . . . . . . . . . . -55C to +125C Supply Voltage with Respect to Ground. . . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . .-0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . .-0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0C to 70C) . . . . . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA) Operating in Free Air. . . . . . . . . . . . . . . .0C to +70C Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC ICC Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Supply Current (Static) Supply Current (Active) Test Conditions IOH = -3.2 mA, VCC = Min, VIN = VIH or VIL IOL = 16 mA, VCC = Min, VIN = VIH or VIL Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VIN = 5.25 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Notes 3, 5) VCC = 5 V, TA = 25C, f = 0 MHz (Note 4) VCC = 5 V, TA = 25C, f = 1 MHz (Note 4) -30 40 45 2.0 0.8 10 -10 10 -10 -160 Min 2.4 0.5 Typ Max Unit V V V V A A A A mA mA mA
Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. This parameter is measured in low-power mode with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled and reset. 5. This parameter is not 100% tested, but is evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
10
MACH211SP-7/10 (Com'l)
CAPACITANCE (Note 1)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance VIN = 2.0 V VOUT = 2.0 V Test Conditions VCC = 5.0 V, TA = 25C f = 1 MHz Typ 6 8 Unit pF pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter Symbol tPD tS tH tCO tWL tWH External Feedback fMAX Maximum Frequency (Note 1) 1/(tS + tCO) -7 Parameter Description Input, I/O, or Feedback to Combinatorial Output (Note 3) Setup Time from Input, I/O, or Feedback to Clock (Note 3) Register Data Hold Time Clock to Output (Note 3) LOW Clock Width HIGH D-type T-type D-type Internal Feedback (fCNT) No Feedback tSL tHL tGO tGWL tPDL tSIR tHIR tICO tICS tWICL tWICH fMAXIR tSIL tHIL tIGO tIGOL tSLL Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate to Combinatorial Output Input Latch Gate to Output Through Transparent Output Latch Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate 7.5 1/(tWL + tWH) T-type 3 100 91 133 125 166.7 5.5 0 7 3 9.5 2 2 11 D-type Input Register Clock to Output Register Setup T-type LOW Input Register Clock Width HIGH 3 166.7 2 2 12 14 8.5 5 100 2 2 14 16 ns MHz ns ns ns ns ns 10 3 11 5 ns ns 9 10 2 2 13 5 12 5 80 74 100 91 100 6.5 0 7 ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns 3 D-type T-type 5.5 6.5 0 4.5 5 Min Max 7.5 6.5 7.5 0 6 Min -10 Max 10 Unit ns ns ns ns ns ns
Setup Time from Input, I/O, or Feedback to Gate Latch Data Hold Time Gate to Output Gate Width LOW Input, I/O, or Feedback to Output Through Transparent Input or Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock to Combinatorial Output
MACH211SP-7/10 (Com'l)
11
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued)
Parameter Symbol tIGS tWIGL tPDLL tAR tARW tARR tAP tAPW tAPR tEA tER tLP tLPS tLPCO tLPEA -7 Parameter Description Input Latch Gate to Output Latch Setup Input Latch Gate Width LOW Input, I/O, or Feedback to Output Through Transparent Input and Output Latches Asynchronous Reset to Registered or Latched Output Asynchronous Reset Width (Note 1) Asynchronous Reset Recovery Time (Note 1) Asynchronous Preset to Registered or Latched Output Asynchronous Preset Width (Note 1) Asynchronous Preset Recovery Time (Note 1) Input, I/O, or Feedback to Output Enable (Note 1) Input, I/O, or Feedback to Output Disable (Note 1) tPD Increase for Powered-down Macrocell (Note 3) tS Increase for Powered-down Macrocell (Note 3) tCO Increase for Powered-down Macrocell (Note 3) tEA Increase for Powered-down Macrocell (Note 3) 5 5 9.5 9.5 10 10 0 10 5 5 9.5 10 10 12 12 10 10 0 10 Min 10 3 12.5 9.5 10 10 15 Max Min 11 5 14 15 -10 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 2. See Switching Test Circuit for test conditions. 3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
12
MACH211SP-7/10 (Com'l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied. . . . . . . . . . . . . . -55C to +125C Supply Voltage with Respect to Ground. . . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . .-0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . .-0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = 0C to 70C) . . . . . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices Ambient Temperature (TA) Operating in Free Air. . . . . . . . . . . . . . . .0C to +70C Supply Voltage (VCC) with Respect to Ground . . . . . . . . +4.75 V to +5.25 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC ICC Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Supply Current (Static) Supply Current (Active) Test Conditions IOH = -3.2 mA, VCC = Min, VIN = VIH or VIL IOL = 16 mA, VCC = Min, VIN = VIH or VIL Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VIN = 5.25 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Notes 3, 5) VCC = 5 V, TA = 25C, f = 0 MHz (Note 4) VCC = 5 V, TA = 25C, f = 1 MHz (Note 4) -30 40 45 2.0 0.8 10 -10 10 -10 -160 Min 2.4 0.5 Typ Max Unit V V V V A A A A mA mA mA
Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. This parameter is measured in low-power mode with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled and reset. 5. This parameter is not 100% tested, but is evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
MACH211SP-12/15/20 (Com'l)
13
CAPACITANCE (Note 1)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance VIN = 2.0 V VOUT = 2.0 V Test Conditions VCC = 5.0 V, TA = 25C f = 1 MHz Typ 6 8 Unit pF pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter Symbol tPD tS tH tCO tWL tWH External Feedback fMAX Maximum Frequency (Note 1) 1/(tS + tCO) -12 Parameter Description Input, I/O, or Feedback to Combinatorial Output (Note 3) Setup Time from Input, I/O, or Feedback to Clock Register Data Hold Time Clock to Output (Note 3) LOW Clock Width HIGH D-type T-type D-type Internal Feedback (fCNT) No Feedback tSL tHL tGO tGWL tPDL tSIR tHIR tICO tICS tWICL tWICH fMAXIR tSIL tHIL Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time 1/(tWL + tWH) T-type 6 66.7 62.5 83.3 76.9 83.3 7 0 10 6 14 2 2 15 12 13 6 6 83.3 2 2 15 16 6 6 83.3 2 2.5 2 2.5 18 20 21 8 8 62.5 2 3 6 17 2 3 23 6 50 47.6 66.6 62.5 83.3 10 0 11 8 22 8 40 38.5 50 47.6 62.5 13 0 12 ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns 6 D-type T-type 7 8 0 8 6 Min Max 12 10 11 0 10 8 Min -15 Max 15 13 14 0 12 Min -20 Max 20 Unit ns ns ns ns ns ns
Setup Time from Input, I/O, or Feedback to Gate Latch Data Hold Time Gate to Output Gate Width LOW Input, I/O, or Feedback to Output Through Transparent Input or Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock to Combinatorial Output Input Register Clock to Output Register D-type Setup T-type LOW Input Register Clock Width HIGH 1/(tWICL + tWICH)
14
MACH211SP-12/15/20 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) (continued)
Parameter Symbol tIGO tIGOL tSLL tIGS tWIGL tPDLL tAR tARW tARR tAP tAPW tAPR tEA tER tLP tLPS tLPCO tLPEA -12 Parameter Description Input Latch Gate to Combinatorial Output Input Latch Gate to Output Through Transparent Output Latch Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate Input Latch Gate to Output Latch Setup Input Latch Gate Width LOW Input, I/O, or Feedback to Output Through Transparent Input and Output Latches Asynchronous Reset to Registered or Latched Output Asynchronous Reset Width (Note 1) Asynchronous Reset Recovery Time (Note 1) Asynchronous Preset to Registered or Latched Output Asynchronous Preset Width (Note 1) Asynchronous Preset Recovery Time (Note 1) Input, I/O, or Feedback to Output Enable (Note 1) Input, I/O, or Feedback to Output Disable (Note 1) tPD Increase for Powered-down Macrocell (Note 3) tS Increase for Powered-down Macrocell (Note 3) tCO Increase for Powered-down Macrocell (Note 3) tEA Increase for Powered-down Macrocell (Note 3) 12 8 15 15 10 10 0 10 12 8 16 15 10 15 15 10 10 0 10 9 13 6 16 16 15 10 20 20 15 15 15 10 10 0 10 Min Max 17 19 12 16 6 19 20 20 15 25 Min -15 Max 20 22 15 21 8 24 25 Min -20 Max 25 27 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 2. See Switching Test Circuit for test conditions. 3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
MACH211SP-12/15/20 (Com'l)
15
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied. . . . . . . . . . . . . . -55C to +125C Supply Voltage with Respect to Ground. . . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . .-0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . .-0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = -40C to +85C). . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
OPERATING RANGES
Industrial (I) Devices Temperature (TA) Operating in Free Air. . . . . . . . . . . . . .-40C to +85C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . +4.5 V to +5.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified
Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC ICC Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Leakage Current Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Supply Current (Static) Supply Current (Active) Test Conditions IOH = -3.2 mA, VCC = Min, VIN = VIH or VIL IOL = 16 mA, VCC = Min, VIN = VIH or VIL Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VIN = 5.25 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Notes 3, 5) VCC = 5 V, TA = 25C, f = 0 MHz (Note 4) VCC = 5 V, TA = 25C, f = 1 MHz (Note 4) -30 40 45 2.0 0.8 10 -10 10 -10 -160 Min 2.4 0.5 Typ Max Unit V V V V A A A A mA mA mA
Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. This parameter is measured in low-power mode with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled and reset. 5. This parameter is not 100% tested, but is evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
16
MACH211SP-10/12 (Ind)
CAPACITANCE (Note 1)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance VIN = 2.0 V VOUT = 2.0 V Test Conditions VCC = 5.0 V, TA = 25C f = 1 MHz Typ 6 8 Unit pF pF
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
Parameter Symbol tPD tS tH tCO tWL tWH External Feedback fMAX Maximum Frequency (Note 1) 1/(tS + tCO) -10 Parameter Description Input, I/O, or Feedback to Combinatorial Output (Note 3) D-type Setup Time from Input, I/O, or Feedback to Clock T-type Register Data Hold Time Clock to Output (Note 3) LOW Clock Width HIGH D-type T-type D-type Internal Feedback (fCNT) No Feedback tSL tHL tGO tGWL tPDL tSIR tHIR tICO tICS tWICL tWICH fMAXIR tSIL tHIL tIGO tIGOL Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate to Combinatorial Output Input Latch Gate to Output Through Transparent Output Latch 1/(tWL + tWH) T-type 5 80 74 100 91 100 6.5 0 8 5 12 2 2 13 D-type Input Register Clock to Output Register Setup T-type LOW Input Register Clock Width HIGH 1/(tWICL + tWICH) 5 100 2 2 14 16 6 80 2.5 3 17 19.5 ns MHz ns ns ns ns 11 5 13 6 ns ns 10 12 2.5 3 16 6 14.5 6 64 59 80 72.5 80 8 0 8.5 ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns 5 7.5 0 6 6 9 0 7.5 ns ns ns ns 6.5 Min Max 10 8 Min -12 Max 12 Unit ns ns
Setup Time from Input, I/O, or Feedback to Gate Latch Data Hold Time Gate to Output Gate Width LOW Input, I/O, or Feedback to Output Through Transparent Input or Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock to Combinatorial Output
MACH211SP-10/12 (Ind)
17
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) (continued)
Parameter Symbol tSLL tIGS tWIGL tPDLL tAR tARW tARR tAP tAPW tAPR tEA tER tLP tLPS tLPCO tLPEA -10 Parameter Description Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate Input Latch Gate to Output Latch Setup Input Latch Gate Width LOW Input, I/O, or Feedback to Output Through Transparent Input and Output Latches Asynchronous Reset to Registered or Latched Output Asynchronous Reset Width (Note 1) Asynchronous Reset Recovery Time (Note 1) Asynchronous Preset to Registered or Latched Output Asynchronous Preset Width (Note 1) Asynchronous Preset Recovery Time (Note 1) Input, I/O, or Feedback to Output Enable (Note 1) Input, I/O, or Feedback to Output Disable (Note 1) tPD Increase for Powered-down Macrocell (Note 3) tS Increase for Powered-down Macrocell (Note 3) tCO Increase for Powered-down Macrocell (Note 3) tEA Increase for Powered-down Macrocell (Note 3) 10 10 15 15 10 10 0 10 10 10 15 12 10 15 15 10 10 0 10 Min 8.5 11 5 14 15 12 10 18 Max Min 10.5 13.5 6 17 19.5 -12 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit for test conditions. 3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
18
MACH211SP-10/12 (Ind)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied. . . . . . . . . . . . . . -55C to +125C Supply Voltage with Respect to Ground. . . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage . . . . . . . . . . . .-0.5 V to VCC + 0.5 V DC Output or I/O Pin Voltage . . . . . . . . . . . . . .-0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V Latchup Current (TA = -40C to 85C) . . . . . . 200 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ.
OPERATING RANGES
Industrial (I) Devices Ambient Temperature (TA) Operating in Free Air. . . . . . . . . . . . . .-40C to +85C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . +4.5 V to +5.5 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
DC CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified
Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC ICC Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Leakage Current Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Supply Current (Static) Supply Current (Active) Test Conditions IOH = -3.2 mA, VCC = Min, VIN = VIH or VIL IOL = 16 mA, VCC = Min, VIN = VIH or VIL Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1) Guaranteed Input Logical LOW Voltage for all Inputs (Note 1) VIN = 5.25 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Notes 3, 5) VCC = 5 V, TA = 25C, f = 0 MHz (Note 4) VCC = 5 V, TA = 25C, f = 1 MHz (Note 4) -30 40 45 2.0 0.8 10 -10 10 -10 -160 Min 2.4 0.5 Typ Max Unit V V V V A A A A mA mA mA
Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 4. This parameter is measured in low-power mode with a 16-bit up/down counter pattern. This pattern is programmed in each PAL block and is capable of being loaded, enabled and reset. 5. This parameter is not 100% tested, but is evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
MACH211SP-14/18/24 (Ind)
19
CAPACITANCE (Note 1)
Parameter Symbol CIN COUT Parameter Description Input Capacitance Output Capacitance VIN = 2.0 V VOUT = 2.0 V Test Conditions VCC = 5.0 V, TA = 25C f = 1 MHz Typ 6 8 Unit pF pF
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
Parameter Symbol tPD tS tH tCO tWL tWH External Feedback fMAX Maximum Frequency (Note 1) 1/(tS + tCO) -14 Parameter Description Input, I/O, or Feedback to Combinatorial Output (Note 3) Setup Time from Input, I/O, or Feedback to Clock Register Data Hold Time Clock to Output (Note 3) LOW Clock Width HIGH D-type T-type D-type Internal Feedback (fCNT) No Feedback tSL tHL tGO tGWL tPDL tSIR tHIR tICO tICS tWICL tWICH fMAXIR tSIL tHIL tIGO Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate to Combinatorial Output 1/(tWL + tWH) T-type 7.5 53 50 61.5 57 66.5 8.5 0 12 7.5 17 2.5 3 18 14.5 16 7.5 7.5 66.5 2.5 3 20.5 18 19.5 7.5 7.5 66.5 2.5 3.5 24 2.5 3.5 22 24 25.5 10 10 50 2.5 4 30 7.5 20.5 2.5 4 28 7.5 40 38 53 44 66.5 12 0 13.5 10 26.5 10 32 30.5 38 34.5 50 16 0 14.5 ns MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns 7.5 D-type T-type 8.5 10 0 10 7.5 Min Max 14.5 12 13.5 0 12 10 Min -18 Max 18 16 17 0 14.5 Min -24 Max 24 Unit ns ns ns ns ns ns
Setup Time from Input, I/O, or Feedback to Gate Latch Data Hold Time Gate to Output Gate Width LOW Input, I/O, or Feedback to Output Through Transparent Input or Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock to Combinatorial Output Input Register Clock to Output Register D-type Setup T-type LOW Input Register Clock Width HIGH 1/(tWICL + tWICH)
20
MACH211SP-14/18/24 (Ind)
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2) (continued)
Parameter Symbol tIGOL tSLL tIGS tWIGL tPDLL tAR tARW tARR tAP tAPW tAPR tEA tER tLP tLPS tLPCO tLPEA -14 Parameter Description Input Latch Gate to Output Through Transparent Output Latch Setup Time from Input, I/O, or Feedback Through Transparent Input Latch to Output Latch Gate Input Latch Gate to Output Latch Setup Input Latch Gate Width LOW Input, I/O, or Feedback to Output Through Transparent Input and Output Latches Asynchronous Reset to Registered or Latched Output Asynchronous Reset Width (Note 1) Asynchronous Reset Recovery Time (Note 1) Asynchronous Preset to Registered or Latched Output Asynchronous Preset Width (Note 1) Asynchronous Preset Recovery Time (Note 1) Input, I/O, or Feedback to Output Enable (Note 1) Input, I/O, or Feedback to Output Disable (Note 1) tPD Increase for Powered-down Macrocell (Note 3) tS Increase for Powered-down Macrocell (Note 3) tCO Increase for Powered-down Macrocell (Note 3) tEA Increase for Powered-down Macrocell (Note 3) 14.5 10 14.5 14.5 10 10 0 10 14.5 10 19.5 18 12 18 18 10 10 0 10 11 16 7.5 19.5 19.5 18 12 24 24 18 24 24 10 10 0 10 Min Max 23 14.5 19.5 7.5 23 24 24 18 30 Min -18 Max 26.5 18 25.5 10 29 30 Min -24 Max 32.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. 2. See Switching Test Circuit for test conditions. 3. If a signal is powered-down, this parameter must be added to its respective high-speed parameter.
MACH211SP-14/18/24 (Ind)
21
TYPICAL ICC CHARACTERISTICS VCC = 5 V, TA = 25C
200 High Speed
150
ICC (mA) 100
Low Power
50
0 0 10 20 30 40 50 60 70 80 90
Frequency (MHz)
20405B-5
The selected "typical" pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register.
22
MACH211SP-7/10/12/15/20
TYPICAL THERMAL CHARACTERISTICS
Measured at 25C ambient. These parameters are not tested.
Parameter Symbol jc ja Typ Parameter Description Thermal impedance, junction to case Thermal impedance, junction to ambient 200 lfpm air jma Thermal impedance, junction to ambient with air flow 400 lfpm air 600 lfpm air 800 lfpm air TQFP 11.3 41 35 33.7 32.6 32 PLCC 4 30.4 18.5 15.9 13.5 12.8 Unit C/W C/W C/W C/W C/W C/W
Plastic jc Considerations
The data listed for plastic jc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the jc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. TQFP thermal measurements are taken with components on a six-layer printed circuit board.
MACH211SP-7/10/12/15/20
23
SWITCHING WAVEFORMS
Input, I/O, or Feedback VT tPD Combinatorial Output VT
20405B-6
Combinatorial Output
Input, I/O, or Feedback tS Clock VT tCO Registered Output
VT tH
Input, I/O, or Feedback tSL Gate tPDL VT Latched Out
VT tHL VT tGO VT
20405B-7
20405B-8
Registered Output
Latched Output
tWH Clock tWL
20405B-9
Gate tGWL
VT
20405B-10
Clock Width
Gate Width
Registered Input tSIR Input Register Clock Combinatorial Output VT tICO
VT tHIR
Registered Input Input Register Clock Output Register Clock
VT
VT
VT
tICS
VT
20405B-11
20405B-12
Registered Input
Input Register to Output Register Setup
Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns-4 ns typical.
24
MACH211SP-7/10/12/15/20
SWITCHING WAVEFORMS
Latched In tSIL Gate
VT tHIL VT tIGO
Combinatorial Output
VT
20405B-13
Latched Input
tPDLL Latched In Latched Out Input Latch Gate tIGOL tSLL VT VT
VT
tIGS Output Latch Gate
20405B-14
Latched Input and Output
Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns-4 ns typical.
MACH211SP-7/10/12/15/20
25
SWITCHING WAVEFORMS
tWICH Clock tWICL VT Input Latch Gate tWIGL VT
20405B-15
20405B-16
Input Register Clock Width
Input Latch Gate Width
tARW Input, I/O, or Feedback tAR Registered Output or Latched Output Clock or Input Latch Gate VT Registered Output or Latched Output tARR VT Clock or Input Latch Gate VT Input, I/O, or Feedback
tAPW VT tAP VT tAPR VT
20405B-17
20405B-18
Asynchronous Reset
Asynchronous Preset
Input, I/O, or Feedback tER Outputs VOH - 0.5 V VOL + 0.5 V
VT tEA VT
20405B-19
Output Disable/Enable
Notes: 1. VT = 1.5 V. 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2 ns-4 ns typical.
26
MACH211SP-7/10/12/15/20
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Must be Steady May Change from H to L May Change from L to H Don't Care, Any Change Permitted Does Not Apply OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
5V
S1
R1 Output R2 CL Test Point
20405B-20
Commercial Specification tPD, tCO tEA tER Closed Z H: Open Z L: Closed H Z: Open L Z: Closed 5 pF 35 pF 300 390 H Z: VOH - 0.5 V L Z: VOL + 0.5 V 1.5 V S1 CL R1 R2 Measured Output Value
* Switching several outputs simultaneously should be avoided for accurate measurement.
MACH211SP-7/10/12/15/20
27
FMAX PARAMETERS
The parameter fMAX is the maximum clock rate at which the device is guaranteed to operate. Because the flexibility inherent in programmable logic devices offers a choice of clocked flip-flop designs, fMAX is specified for three types of synchronous designs. The first type of design is a state machine with feedback signals sent off-chip. This external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. The slowest path defining the period is the sum of the clock-to-output time and the input setup time for the external signals (tS + tCO). The reciprocal, fMAX, is the maximum frequency with external feedback or in conjunction with an equivalent speed device. This fMAX is designated "fMAX external." The second type of design is a single-chip state machine with internal feedback only. In this case, flip-flop inputs are defined by the device inputs and flip-flop outputs. Under these conditions, the period is limited by the internal delay from the flip-flop outputs through the internal feedback and logic to the flip-flop inputs. This fMAX is designated "fMAX internal". A simple internal counter is a good example of this type of design; therefore, this parameter is sometimes called "fCNT."
CLK
The third type of design is a simple data path application. In this case, input data is presented to the flip-flop and clocked through; no feedback is employed. Under these conditions, the period is limited by the sum of the data setup time and the data hold time (tS + tH). However, a lower limit for the period of each fMAX type is the minimum clock period (tWH + tWL). Usually, this minimum clock period determines the period for the third fMAX, designated "fMAX no feedback." For devices with input registers, one additional fMAX parameter is specified: fMAXIR. Because this involves no feedback, it is calculated the same way as fMAX no feedback. The minimum period will be limited either by the sum of the setup and hold times (tSIR + tHIR) or the sum of the clock widths (tWICL + t WICH ). The clock widths are normally the limiting parameters, so that fMAXIR is specified as 1/(tWICL + tWICH). Note that if both input and output registers are use in the same path, the overall frequency will be limited by tICS. All frequencies except fMAX internal are calculated from other measured AC parameters. fMAX internal is measured directly.
CLK
(SECOND CHIP) LOGIC REGISTER LOGIC REGISTER
tS
tCO fMAX External; 1/(tS + tCO) CLK
tS fMAX Internal (fCNT) CLK
LOGIC
REGISTER
REGISTER
LOGIC
tS fMAX No Feedback; 1/(tS + tH) or 1/(tWH + tWL)
tSIR
tHIR
fMAXIR; 1/(tSIR + tHIR) or 1/(tWICL + tWICH)
20405B-21
28
MACH211SP-7/10/12/15/20
ENDURANCE CHARACTERISTICS
The MACH families are manufactured using AMD's advanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory.
Endurance Characteristics
Parameter Symbol tDR N Parameter Description Min Pattern Data Retention Time 20 Max Reprogramming Cycles 100 Years Cycles Max Operating Temperature Normal Programming Conditions Min 10 Units Years Test Conditions Max Storage Temperature
MACH211SP-7/10/12/15/20
29
INPUT/OUTPUT EQUIVALENT SCHEMATICS
VCC
100 k 1 k VCC
ESD Protection
Input
VCC
VCC
100 k
1 k
Preload Circuitry
Feedback Input I/O
20405B-22
30
MACH211SP-7/10/12/15/20
POWER-UP RESET
The MACH devices have been designed with the capability to reset during system power-up. Following power-up, all flip-flops will be reset to LOW. The output state will depend on the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up
Parameter Symbol tPR tS tWL Parameter Descriptions Power-Up Reset Time Input or Feedback Setup Time See Switching Characteristics Clock Width LOW
reset and the wide range of ways VCC can rise to its steady state, two conditions are required to insure a valid power-up reset. These conditions are: 1. The VCC rise must be monotonic. 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met.
Max 10 Unit s
VCC Power 4V tPR Registered Output tS Clock
tWL
20405B-23
Power-Up Reset Waveform
MACH211SP-7/10/12/15/20
31
DEVELOPMENT SYSTEMS (subject to change)
For more information on the products listed below, please consult the AMD FusionPLD Catalog.
MANUFACTURER Advanced Micro Devices, Inc. P.O. Box 3453, MS 1028 Sunnyvale, CA 94088-3543 (800) 222-9323 or (408) 732-2400 Advanced Micro Devices, Inc. P.O. Box 3453, MS 1028 Sunnyvale, CA 94088-3543 (800) 222-9323 or (408) 732-2400 Advanced Micro Devices, Inc. P.O. Box 3453, MS 1028 Sunnyvale, CA 94088-3543 (800) 222-9323 or (408) 732-2400 Advanced Micro Devices, Inc. P.O. Box 3453, MS 1028 Sunnyvale, CA 94088-3543 (800) 222-9323 or (408) 732-2400 Cadence Design Systems 555 River Oaks Pkwy San Jose, CA 95134 (408) 943-1234 Data I/O Corporation 10525 Willows Road N.E. P.O. Box 97046 Redmond, WA 98073-9746 (800) 332-8246 or (206) 881-6444 Mentor Graphics Corp. 8005 S.W. Boeckman Rd. Wilsonville, OR 97070-7777 (800) 547-3000 or (503) 685-7000 MicroSim Corp. 20 Fairbanks Irvine, CA 92718 (714) 770-3022 MINC Incorporated 6755 Earl Drive, Suite 200 Colorado Springs, CO 80918 (800) 755-FPGA or (719) 590-1155 SUSIE-CAD 10000 Nevada Highway, Suite 201 Boulder City, NV 89005 (702) 293-2271 Synopsys Logic Modeling 19500 NW Gibbs Dr. P.O. Box 310 Beaverton, OR 97075 (503) 690-6900 Teradyne EDA 321 Harrison Ave. Boston, MA 02118 (800) 777-2432 or (617) 422-2793 SOFTWARE DEVELOPMENT SYSTEMS MACHXL(R) Software Ver. 3.0
Design Center/AMD Software
AMD-ABEL Software Data I/O MACH Fitters
PROdeveloper/AMD Software PROsynthesis/AMD Software PLDTM Designer Verilog, LeapFrog, RapidSim Simulators Ver. 9504
ABELTM Software SynarioTM Software
PLDSynthesisTM II QuickSim Simulator
Design Center Software
PLDesignerTM-XL Software
SUSIETM Simulator
SmartModel(R) Library
MultiSIM Interactive Simulator LASAR
32
MACH211SP-7/10/12/15/20
DEVELOPMENT SYSTEMS (subject to change) (continued)
MANUFACTURER Viewlogic Systems, Inc. 293 Boston Post Road West Marlboro, MA 01752 (800) 442-4660 or (508) 480-0881 MANUFACTURER Acugen Software, Inc. 427-3 Amherst St., Suite 391 Nashua, NH 03063 (603) 891-1995 iNt GmbH Busenstrasse 6 D-8033 Martinsried, Munich, Germany (87) 857-6667 SOFTWARE DEVELOPMENT SYSTEMS ViewPLD or PROPLD (Requires PROSim Simulator MACH Fitter) ViewSim Simulator TEST GENERATION SYSTEM
ATGENTM Test Generation Software
PLDCheck 90
Advanced Micro Devices is not responsible for any information relating to the products of third parties. The inclusion of such information is not a representation nor an endorsement by AMD of these products.
MACH211SP-7/10/12/15/20
33
APPROVED PROGRAMMERS (subject to change)
For more information on the products listed below, please consult the AMD FusionPLD Catalog.
MANUFACTURER Advin Systems, Inc. 1050-L East Duane Ave. Sunnyvale, CA 94086 (408) 243-7000 BP Microsystems 100 N. Post Oak Rd. Houston, TX 77055-7237 (800) 225-2102 or (713) 688-4600 Data I/O Corporation 10525 Willows Road N.E. P.O. Box 97046 Redmond, WA 98073-9746 (800) 332-8246 or (206) 881-6444 Hi/Lo 4F, No. 2, Sec. 5, Ming Shoh E. Rd. Taipei, Taiwan Logical Devices Inc./Digelec 692 S. Military Trail Deerfield Beach, FL 33442 (800) 331-7766 or (305) 428-6868 SMS North America, Inc. 16522 NE 135th Place Redmond, WA 98052 (800) 722-4122 or SMS lm Grund 15 D-7988 Vangen Im Allgau, Germany 07522-5018 Stag Microsystems Inc. 1600 Wyatt Dr. Suite 3 Santa Clara, CA 95054 (408) 988-1118 or Stag House Martinfield, Welwyn Garden City Herfordshire UK AL7 1JT 707-332148 System General 510 S. Park Victoria Dr. Milpitas, CA 95035 (408) 263-6667 or 3F, No. 1, Alley 8, Lane 45 Bao Shing Rd., Shin Diau Taipei, Taiwan 2-917-3005 PROGRAMMER CONFIGURATION
Pilot U84
BP1148
BP1200
BP2100
UniSiteTM
Model 2900
Model 3900
AutoSite
ALL-07
FLEX-700
ALLPROTM-88
Sprint
Expert
Multisite
Stag Quazar Stag Eclipse
Turpro-1
FX
TX
34
MACH211SP-7/10/12/15/20
APPROVED ON-BOARD PROGRAMMERS
MANUFACTURER Corelis, Inc. 12607 Hidden Creek Way, Suite H Cerritos, California 70703 (310) 926-6727 Advanced Micro Devices P.O. Box 3453, MS-1028 Sunnyvale, CA 94088-3453 (800) 222-9323 PROGRAMMER CONFIGURATION
JTAG PROG
MACHpro
PROGRAMMER SOCKET ADAPTERS (subject to change)
MANUFACTURER California Integration Technologies 656 Main Street Placerville, CA 95667 (916) 626-6168 EDI Corporation P.O. Box 366 Patterson, CA 95363 (209) 892-3270 Emulation Technology 2344 Walsh Ave., Bldg. F Santa Clara, CA 95051 (408) 982-0660 Logical Systems Corp. P.O. Box 6184 Syracuse, NY 13217-6184 (315) 478-0722 Procon Technologies, Inc. 1333 Lawrence Expwy, Suite 207 Santa Clara, CA 95051 (408) 246-4456 PART NUMBER
Contact Manufacturer
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Contact Manufacturer
MACH211SP-7/10/12/15/20
35
PHYSICAL DIMENSIONS* PL 044 44-Pin Plastic Leaded Chip Carrier (measured in inches)
.062 .083
.685 .695
.650 .656
.042 .056
Pin 1 I.D. .685 .695 .650 .656 .500 .590 REF .630
.013 .021
.026 .032
.050 REF
.009 .015
.090 .120 .165 .180
SEATING PLANE
TOP VIEW
SIDE VIEW
16-038-SQ PL 044 DA78 6-28-94 ae
* For reference only. BSC is an ANSI standard for Basic Space Centering.
36
MACH211SP-7/10/12/15/20
PHYSICAL DIMENSIONS PQT044 44-Pin Thin Quad Flat Pack (measured in millimeters)
44
1
11.80 12.20 9.80 10.20
9.80 10.20 11.80 12.20
11 - 13 0.95 1.05 1.20 MAX
16-038-PQT-2 PQT 44 7-11-95 ae
1.00 REF.
0.30 0.45
0.80 BSC
11 - 13
Trademarks Copyright (c) 1996 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, MACH, and PAL are registered trademarks of Advanced Micro Devices, Inc. Bus-Friendly is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
MACH211SP-7/10/12/15/20
37

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